Gasgoo Munich- In 2026, smart driving is speeding out of the premium tier. Urban NOA is rapidly trickling down from high-end models to mainstream price points. Yet a glaring mismatch remains: AI models iterate by the month, while vehicle development cycles run by the year—and a car stays with its owner far longer than either. Can a chip chosen today shoulder the models of tomorrow?
On October 29, a launch event in Suzhou placed "large models defining chips" front and center. As figures like 700 TOPS, 98.7% compute utilization, and 200,000 units shipped were laid out, a new technical roadmap snapped into focus: rather than building a chip first and forcing models to adapt, understand the large model first, then design the silicon around it.
Image Source: XHEART (same below)
Three Hard Questions Large Models Pose to Chips
In the era of large models, what kind of chip do we actually need? For Li Zonglin, CEO of XHEART, the answer determines whether model breakthroughs translate into real product gains—and when smarter autonomy will weave into everyday life.
The answer starts with how autonomous driving algorithms have evolved.
Older autonomous systems were essentially stitched together from small models: one for perception, another for prediction, and a third for planning. The division of labor looked clean, but that was exactly the problem. As information passed between models, dimensions were compressed and vital data was lost, dragging down utilization. Small models also carry a low performance ceiling and weak generalization.
"The ceiling of small models is, at its core, the cognitive ceiling of their human designers," Li noted. In the small-model era, autonomy was fundamentally a brain-driven system: engineers wrote the top-level rules, and machines executed them. Now, as Transformer-based end-to-end large models mature, massive datasets are being leveraged efficiently for the first time. The paradigm is shifting from "human-driven" to "data-driven."
As the model changes, so do the exams for the chip.
Li frames them as three distinct challenges. First, can compute actually deliver in a real system? Users care little for paper specs; they need inference fast enough and judgments timely enough under deployed, mass-produced models. Second, can a chip designed today keep pace with tomorrow's models? Without architectural foresight and headroom, OTA upgrades will hit a hard ceiling. Third, can it deliver capability without runaway power draw? Thermal budgets in vehicles are unforgiving—solutions that scale compute by spiking energy consumption will never see mass adoption.
"These three questions must be answered together," Li argued. His logic: start with the actual demands of a large model and work backward to organize compute, storage, and data flow—directing silicon resources precisely where the model needs them. That is what "large models defining chips" means.
This wasn't a pivot on a whim. When the team—veterans with one or two decades in the chip industry—decided to start up in 2023, their founding discipline was caution: would the chip they built years later actually be what the market wanted? They chose to cut their teeth on automotive, a domain with the most unforgiving demands on performance, cost, and safety, to validate their thesis.
XHEART isn't alone in this conviction. At the event, Cao Xudong, CEO of strategic partner Momenta, publicly unveiled his company's third core insight for the first time: large models define chips.
Scaling to L4, he argued, will demand models with at least 10 billion—and likely 100 billion—parameters. General-purpose chips cannot simultaneously satisfy power, automotive-grade reliability, and cost constraints. He calls this the "impossible triangle of general-purpose chips." "Using them is like strapping a massive GPU server into a car," Cao said. "The power draw is untenable, and reliability falls short of automotive standards."
Purpose-built silicon defined by large models can deliver 10 times the overall performance of general-purpose chips, Cao noted. Back when Momenta was founded, the company calculated that solving millions of edge cases and supporting scaled L4 would require roughly 100 billion kilometers of real-world data—the equivalent of 1 million passenger vehicles driving non-stop for a full year.
In this framework, cars are merely the starting point. The team's second bet: to equip more brands and vehicle tiers with superior autonomy—making it both accessible and affordable—chips must simultaneously nail performance, power efficiency, and cost.
On one side, 100 billion kilometers of data feeding the system; on the other, 100 billion parameters of model appetite. As the main battleground of autonomy shifts from "rules" to "data," the power to define chips is quietly changing hands.
Turning Compute into True Capability
The star of the event was XHEART's mass-production-ready large-model chip, the X7 Ultra.
"First, remember this number: 700 TOPS of large-model compute," Li said. Yet more telling than the raw figure is the benchmarking approach. There were no lab benchmarks—only evaluations against real, mass-produced autonomous driving models. After quantized deployment, the model output achieved a similarity of over 99.99% to the trained FP32 floating-point model.
"Lab results often diverge sharply from the performance and feel of production models." That means model structures can't be casually altered, compute precision must hold, and the driving experience carries no compromises.
To make large models run fast and stable in production, the X7 Ultra's architecture tackles several fronts.
Most striking is the oversized NPU core designed specifically for large models. As models consolidate, the architecture must be built for consolidation. Li likened it to moving a scattered team from separate offices into a single war room. Data interaction leaps from the 100-GB/s scale typical of small cores to the TB/s scale within the mega-core—a orders-of-magnitude jump in interconnect speed. Paired with high-capacity, high-concurrency multi-level caching, the design "cuts wait times for compute and shortens detours for data."
Complementing the mega-core are dedicated acceleration engines for critical operators. Early NPUs, built for convolutional networks, had to offload unsupported Transformer operators to other processors—triggering task switches and extra memory reads. Back in 2023, the silicon and algorithm teams mapped the evolving mainline model to forecast which calculations would grow most critical. XHEART built custom hardware accelerators for high-frequency, latency-sensitive operators like ReLU, Softmax, and Transpose, paired with peak-efficiency buffer registers. The chip also natively supports high-precision floating-point vector compute, ensuring "critical math runs fast and exact."
On that foundation, the X7 Ultra unlocks deeper hardware parallelism and overhauls the AI toolchain. In production-model tests, the X7 Ultra's NPU hit 98.7% compute utilization. Compute and weight loading run in parallel; while one batch executes, the next is already staged. The toolchain's standout feature is "full-network fusion." Traditional inference repeatedly writes and reads intermediate results to external memory. The X7 Ultra extends optimization across the entire network, orchestrating all layers and branches into a single, network-wide macro-operator—achieving zero-copy memory use across the whole graph.
Hard metrics follow. Official tests show that at equivalent large-model performance, the X7 Ultra cuts memory bandwidth consumption by 80% and doubles inference energy efficiency compared to industry flagships.
If the NPU leads the charge, the Armv9 automotive-grade CPU—China's first to hit mass production—serves as the "super dispatcher." It entered production in a customer vehicle this March, posting a 20% performance gain and 10% efficiency gain over the prior generation. A new SVE2 vector engine bolsters DSP performance, while a large-cluster architecture tightens multi-core coordination and L3 cache efficiency.
Beyond main control, deep heterogeneous compute proves equally vital. A LiDAR processing accelerator supports bandwidths up to 20 million points per second—enough for thousand-line LiDAR. For cameras, XHEART ignores "deceptive" average latency, zeroing in on jitter. If typical processing takes 30 milliseconds but jitter ranges between 20 and 50 milliseconds, that 50-millisecond spike marks the safety floor. Leveraging a local high-performance multi-core processor, the chip delivers 100% better camera processing stability than rivals.
Underpinning it all is the safety foundation. The X7 Ultra meets ISO 26262 ASIL-B functional safety, while its embedded MCU clears the top-tier ASIL-D certification; information security complies with GM/T 0028 Level 2. Yet the team stresses that hardware safety is merely the "body." Most autonomy failures stem from breaching the model's algorithmic boundaries. "Driving safety"—underpinned by compute headroom and iteration space—is the "brain."
Autonomy's Moore's Law Kicks into Higher Gear
A chip's worth ultimately comes down to real vehicles, real models, and real roads. Adaptation speed on the customer side tells the story. In a roundtable, Cao drew a contrast: in the general-purpose chip era, getting models to "run, run stable, run right, and run well" took three to six months, sometimes six to twelve. On the X7, it took just 27 days. "Because from model design to chip design, from feature design to verification, it was all done before tape-out."
Commercial data is even more blunt. The X7 series has been in production for eight months, shipping over 200,000 units across 10 mass-produced models and securing orders from over 40 vehicle programs. An L3/L4 compute platform built on dual X7 chips has already won multiple design contracts. Its unified dual-brain architecture, backed by triple redundancy in power, sensors, and communication, supports both L3 and L4.
The event also revealed core targets for the next-generation X9: 3,000 TOPS of large-model compute and 700 GB/s of single-chip memory bandwidth, slated for 2027. By scaling compute and memory access in lockstep, the X9 will keep pushing hardware-software co-design around next-generation world models.
Chip iterations are laying the groundwork for model leaps.
Cao announced that, powered by the X7 Ultra, Momenta's next-generation world model has expanded to five times the parameter scale, with a 5x safety boost. The capacity to "reason over everything" is starting to emerge.
Training a world model rests on three pillars: pre-training to absorb the physics of the real world, mid-training to inject driving common sense, and post-training to align with expert drivers. Add in low-cost simulation for edge cases and reinforcement learning that hones skills through positive and negative feedback, and the model is learning to predict the future continuously.
Underwriting it all is data scale. Momenta has surpassed 1.4 million production vehicles; the latest 100,000 rolled off lines in under a month. Cumulative driving distance has hit 20 billion kilometers—equivalent to 25,000 round trips to the Moon, or 510,000 laps around the equator. In test videos of reverse avoidance and multi-point turns, vehicles weave through gaps measured in centimeters, "matching or even besting veteran human drivers."
The same world model is also being validated in robotaxi and robotruck deployments. The robotaxi fleet has secured testing and operation permits in Suzhou, Shanghai, Abu Dhabi, and Munich.
Hence a bolder thesis: large-model chips are accelerating autonomy's Moore's Law.
From 2022 to 2026, the autonomous driving experience roughly doubled in quality every two years—a trajectory punctuated by the urban NOA explosion in 2024. Propelled by large-model-defined chips, that cadence is shifting from "10x every two years" to "10x every year." On-vehicle model scale could swell by 10 to 100 times over the next two years.
Cao projects 2028 as the likely inflection point for L3/L4, with scaled deployment arriving in 2030. By the end of 2028, top industry players could achieve 10 times the safety of human driving; by 2030, 100 times.
Wan Gang, honorary chairman of the China Association for Science and Technology, told the 2026 World Intelligent Connected Vehicle Conference that L3 autonomy penetration is expected to top 35% by 2030. Jack Dongarra offered a reminder: three decades ago, floating-point operations were expensive; today, the scarcest resource is data movement. Chip benchmarks must be rebuilt accordingly. "The right chip is the one that helps the whole system reliably finish the job—not the one with the highest peak numbers."
A SAIC executive at the event offered the automaker's perspective: consumers pay for experience, not specs. In the large-model era, a chip must be an all-rounder—automotive-grade reliable, potent in real scenarios, power-frugal, and cost-controlled.
From a race for peak specs to a race for usable compute, from "chips defining models" to "models defining chips"—the winning hand in autonomy silicon's second half has changed. As purpose-built architectures let larger models run on more cars at lower cost, the day high-level autonomy truly becomes both accessible and affordable may arrive sooner than anyone expected.
